SI4134DY www.vishay.com vishay siliconix s15-2154-rev. d, 07-sep-15 1 document number: 68999 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n-channel 30 v (d-s) mosfet ordering information: SI4134DY-t1-e3 (lead (pb)-free) SI4134DY-t1-ge3 (lead (pb)-free and halogen-free) features ? trenchfet ? power mosfet ? 100 % r g and uis tested ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ?dc/dc conversion - notebook system power notes a. based on t c = 25 c. b. surface mounted on 1" x 1" fr4 board. c. t = 10 s. d. maximum under steady state conditions is 85 c/w. product summary v ds (v) r ds(on) ( ) max. i d (a) a q g (typ.) 30 0.0140 at v gs = 10 v 14 7.3 nc 0.0175 at v gs = 4.5 v 12.5 top view s o-8 s in g le 1 s 2 s 3 s s s g d 7 d 6 d 5 d 8 available n-channel mosfet g d s absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 30 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 14 a t c = 70 c 11.2 t a = 25 c 9.9 b, c t a = 70 c 7.9 b, c pulsed drain current (t = 300 s) i dm 50 continuous source-drain diode current t c = 25 c i s 4.1 t a = 25 c 2 b, c single pulse avalanche current l = 0.1 mh i as 15 avalanche energy e as 11.25 mj maximum power dissipation t c = 25 c p d 5 w t c = 70 c 3.2 t a = 25 c 2.5 b, c t a = 70 c 1.6 b, c operating junction and storage temperature range t j , t stg -55 to +150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient b, d t 10 s r thja 38 50 c/w maximum junction-to-foot (drain) steady state r thjf 20 25
SI4134DY www.vishay.com vishay siliconix s15-2154-rev. d, 07-sep-15 2 document number: 68999 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not su bject to production testing. stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 30 - - v v ds temperature coefficient v ds /t j i d = 250 a -33- mv/c v gs(th) temperature coefficient v gs(th) /t j --5- gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.2 1.8 2.5 v gate-source leakage i gss v ds = 0 v, v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = 30 v, v gs = 0 v - - 1 a v ds = 30 v, v gs = 0 v, t j = 55 c - - 10 on-state drain current a i d(on) v ds 5 v, v gs = 10 v 20 - - a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 10 a - 0.0115 0.0140 v gs = 4.5 v, i d = 7 a - 0.0145 0.0175 forward transconductance a g fs v ds = 15 v, i d = 10 a - 24 - s dynamic b input capacitance c iss v ds = 15 v, v gs = 0 v, f = 1 mhz - 846 - pf output capacitance c oss - 187 - reverse transfer capacitance c rss -72- total gate charge q g v ds = 15 v, v gs = 10 v, i d = 10 a - 15.4 23 nc v ds = 15 v, v gs = 4.5 v, i d = 10 a -7.311 gate-source charge q gs -2.3- gate-drain charge q gd -2.2- gate resistance r g f = 1 mhz 0.2 0.8 1.6 turn-on delay time t d(on) v dd = 15 v, r l = 1.5 i d ? 10 a, v gen = 4.5 v, r g = 1 -1530 ns rise time t r -1224 turn-off delay time t d(off) -1326 fall time t f -1020 turn-on delay time t d(on) v dd = 15 v, r l = 1.5 i d ? 10 a, v gen = 10 v, r g = 1 -918 rise time t r -918 turn-off delay time t d(off) -1428 fall time t f -816 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c - - 4.2 a pulse diode forward current a i sm --50 body diode voltage v sd i s = 3 a - 0.78 1.2 v body diode reverse recovery time t rr i f = 10 a, di/dt = 100 a/s, t j = 25 c -1734ns body diode reverse recovery charge q rr - 9.5 19 nc reverse recovery fall time t a -10- ns reverse recovery rise time t b -7-
SI4134DY www.vishay.com vishay siliconix s15-2154-rev. d, 07-sep-15 3 document number: 68999 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) output characteristics on-resistance vs. drain current and gate voltage gate charge transfer characteristics capacitance on-resistance vs. junction temperature 0 10 20 30 40 50 0.0 0.5 1.0 1.5 2.0 2.5 v gs = 10 v thru 5 v v gs =3v v gs =4v v ds - drain-to-source voltage (v) - drain current (a) i d 0.005 0.010 0.015 0.020 0.025 0 1020304050 v gs =10v v gs =4.5v - on-resistance ( ) r ds(on) i d - drain current (a) - gate-to-sou rce v oltage ( v) q g - total gate charge (nc) v gs 0 2 4 6 8 10 0.0 3.2 6.4 9.6 12.8 16.0 v ds =20v i d =10a v ds =15v v ds =10v 0 2 4 6 8 012345 t c =25 c t c = 125 c t c = - 55 c v gs - gate-to-source voltage (v) - drain current (a) i d c rss 0 220 440 660 880 1100 0 5 10 15 20 25 30 c iss c oss v ds - drain-to-source voltage (v) c - capacitance (pf) 0.6 0.8 1.0 1.2 1.4 1.6 1.8 - 50 - 25 0 25 50 75 100 125 150 i d =10a v gs =4.5v v gs =10v t j - junction temperature (c) ( n ormalized) - on-resistance r ds(on)
SI4134DY www.vishay.com vishay siliconix s15-2154-rev. d, 07-sep-15 4 document number: 68999 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) source-drain diode forward voltage threshold voltage on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient safe operating area, junction-to-ambient 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1 0.01 0.001 0.1 10 100 t j = 150 c t j = 25 c v sd - source-to-drain voltage (v) - source current (a) i s - 0.8 - 0.6 - 0.4 - 0.2 0 0.2 0.4 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a i d =5ma variance (v) v gs(th) t j - temperature (c) 0.00 0.01 0.02 0.03 0.04 0.05 0.06 012345678910 t j = 25 c t j = 125 c i d =10a - on-resistance ( ) r ds(on) v gs - gate-to-source voltage (v) 0 16 32 48 64 80 0 1 1 1 0 0 . 00.010.1 time (s) power (w) v ds - drain-to-source voltage (v) *v gs > minimum v gs at which r ds(on) is specified - drain cu rrent (a) i d 100 1 0.1 1 10 100 0.01 10 0.1 t a = 25 c single pulse 1s 10 s limited by r ds(on) * bvdss limited 1ms 10 ms 100 ms dc
SI4134DY www.vishay.com vishay siliconix s15-2154-rev. d, 07-sep-15 5 document number: 68999 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) current derating a power, junction-to-foot power derating, junction-to-ambient note a. the power dissipation p d is based on t j (max.) = 150 c, using junction-t o-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the cu rrent rating, when this rating falls below the package limit. t c - case temperature (c) i d - drain current (a) 0.0 3.2 6.4 9.6 12.8 16.0 0 25 50 75 100 125 150 0.0 1.2 2.4 3.6 4.8 6.0 0 25 50 75 100 125 150 t c - case temperature (c) po wer (w) 0.0 0.4 0.8 1.2 1.6 2.0 0 25 50 75 100 125 150 t a - ambient temperature (c) po wer (w)
SI4134DY www.vishay.com vishay siliconix s15-2154-rev. d, 07-sep-15 6 document number: 68999 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) normalized thermal transient impedance, junction-to-ambient normalized thermal transient impedance, junction-to-foot vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?68999 . 0.2 0.1 t 1 t 2 n otes: p dm 1. duty cycle, d = 2. per unit base = r thja = 85 c/w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. surface mounted duty cycle = 0.5 single pulse 0.02 0.05 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 square wave pulse duration (s) n ormalized effective transient thermal impedance 0.1 0.01 1 10 -3 10 -2 0 1 1 10 -1 10 -4 0.2 0.1 duty cycle = 0.5 square wave pulse duration (s) n ormalized effective transient thermal impedance 1 0.1 0.01 0.05 0.02 single pulse
vishay siliconix package information document number: 71192 11-sep-06 www.vishay.com 1 dim millimeters inches min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q0808 s 0.44 0.64 0.018 0.026 ecn: c-06527-rev. i, 11-sep-06 dwg: 5498 4 3 1 2 5 6 8 7 h e h x 45 c all le a d s q 0.101 mm 0.004" l ba 1 a e d 0.25 mm (g a ge pl a ne) s oic (narrow): 8-lead jedec p a rt n u m b er: m s -012 s
vishay siliconix trenchfet ? power mosfets application note 808 mounting little foot ? , so-8 power mosfets application note document number: 70740 www.vishay.com revision: 18-jun-07 1 wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footpr int of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawin g access for vishay siliconix mosfets, ( http://www.vishay.com/ppg?72286 ), for the basis of the pad design for a little foot so-8 power mosfet. in converting this recommended minimum pad to the pad set for a power mosfet, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. in the case of the so-8 p ackage, the thermal connections are very simple. pins 5, 6, 7, and 8 are the drain of the mosfet for a single mosfet package and are connected together. in a dual package, pi ns 5 and 6 are one drain, and pins 7 and 8 are the other drain. for a small-signal device or integrated circuit, typical co nnections would be made with traces that are 0.020 inches wi de. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copp er may be adequate to carry the current required for the a pplication, but it presents a large thermal impedance. also , heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources wh en looking at heat spread on the pc board. figure 1. single mosfet so-8 pad pattern with copper spreading figure 2. dual mosfet so-8 pad pattern with copper spreading the minimum recommended pad patterns for the single-mosfet so-8 with copp er spreading (figure 1) and dual-mosfet so-8 with copper spreading (figure 2) show the starting point for utilizing th e board area available for the heat-spreading copper. to creat e this pattern, a plane of copper overlies the drain pins . the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat fr om the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. these patterns use all the available area underneath the body for this purpose. since surface-mounted packag es are small, and reflow soldering is the most comm on way in which these are affixed to the pc board, ?t hermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint wi th the copper plane on the drain pins, the solder mask ge neration occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum pow er trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.196 5.0 0.2 88 7.3 0.050 1.27 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.0 88 2.25 0.2 88 7.3 0.050 1.27 0.0 88 2.25
application note 826 vishay siliconix www.vishay.com document number: 72606 22 revision: 21-jan-08 application note recommended minimum pads for so-8 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.172 (4.369) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) return to index return to index
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